发明名称 パルス化したサンプルバイアスを用いる、半導体構造をエッチングするためのパルス化プラズマシステム
摘要 <p>A pulsed plasma system with pulsed sample bias for etching semiconductor structures is described. In one embodiment, a portion of a sample is removed by applying a pulsed plasma process, wherein the pulsed plasma process comprises a plurality of duty cycles. A negative bias is applied to the sample during the ON state of each duty cycle, while a zero bias is applied to the sample during the OFF state of each duty cycle. In another embodiment, a first portion of a sample is removed by applying a continuous plasma process. The continuous plasma process is then terminated and a second portion of the sample is removed by applying a pulsed plasma process.</p>
申请公布号 JP5774071(B2) 申请公布日期 2015.09.02
申请号 JP20130194148 申请日期 2013.09.19
申请人 发明人
分类号 H01L21/3065 主分类号 H01L21/3065
代理机构 代理人
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