Contact techniques and configurations for reducing parasitic resistance in nanowire transistors

摘要

Embodiments of the present disclosure provide contact techniques and configurations for reducing parasitic resistance in nanowire transistors. In one embodiment, an apparatus includes a semiconductor substrate, an isolation layer formed on the semiconductor substrate, a channel layer including nanowire material formed on the isolation layer to provide a channel for a transistor, and a contact coupled with the channel layer, the contact being configured to surround, in at least one planar dimension, nanowire material of the channel layer and to provide a source terminal or drain terminal for the transistor.

主权项

1. An apparatus comprising:
a semiconductor substrate; an isolation layer formed on the semiconductor substrate; a channel layer including nanowire material formed on the isolation layer to provide a channel for a transistor; a contact coupled with the channel layer, the contact being configured to surround, in at least one planar dimension, nanowire material of the channel layer and to provide a source terminal or drain terminal for the transistor; and an epitaxial film disposed on and epitaxially coupled with the channel layer, the epitaxial film surrounding, in the at least one planar dimension, the nanowire material of the channel layer and disposed between the nanowire material of the channel layer and material of the contact, wherein the nanowire material of the channel layer includes N-type or P-type semiconductor material and the epitaxial film includes a group III-V semiconductor material and has a thickness between 50 Angstroms and 1000 Angstroms.