发明名称 |
Stress migration mitigation |
摘要 |
A computer-implemented method of configuring a semiconductor device includes identifying an interconnect having an interconnect path length greater than a stress-induced void formation characteristic length of the semiconductor device, and placing, with a processor, a conductive structure adjacent the interconnect to define a pair of segments of the interconnect. Each segment has a length no greater than the stress-induced void formation characteristic length of the interconnect, and the conductive structure is selected from the group consisting of a decoy via connected to the interconnect, a floating tile disposed along the interconnect, a tab that laterally extends outward from the interconnect, and a jumper from a first metal layer in which the interconnect is disposed to a second metal layer. |
申请公布号 |
US9122829(B2) |
申请公布日期 |
2015.09.01 |
申请号 |
US201313956044 |
申请日期 |
2013.07.31 |
申请人 |
Freescale Semiconductor, Inc. |
发明人 |
Reber Douglas M.;Shroff Mehul D.;Travis Edward O. |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
Lempia Summerfield Katz LLC |
代理人 |
Lempia Summerfield Katz LLC |
主权项 |
1. A computer-implemented method of configuring a semiconductor device, the method comprising:
identifying an interconnect having an interconnect path length greater than a stress-induced void formation characteristic length of the semiconductor device; and placing, with a processor, a conductive structure adjacent the interconnect to define a pair of segments of the interconnect; wherein each segment has a length no greater than the stress-induced void formation characteristic length of the interconnect; and wherein the conductive structure is selected from the group consisting of a decoy via connected to the interconnect, a floating tile disposed along the interconnect, a tab that laterally extends outward from the interconnect, and a jumper from a first metal layer in which the interconnect is disposed to a second metal layer. |
地址 |
Austin TX US |