Clock doubler including duty cycle correction

摘要

Exemplary embodiments are related to a clock doubler. A device may include a duty cycle correction circuit configured to receive an input clock signal and convey a corrected clock signal. The duty cycle correction circuit may include a first circuit to convey an output voltage during a first cycle of the input clock signal and correct a current mismatch of the first circuit during a second cycle of the input clock signal. The duty cycle correction circuit may also include a second circuit to convey the output voltage during the second cycle and correct a current mismatch of the second circuit during the first cycle. Further, the device may include a clock generator for receiving the corrected clock signal and generating an output clock.

主权项

1. A device, comprising:
a duty cycle correction circuit configured to receive an input clock signal and convey a corrected clock signal, the duty cycle correction circuit including:
a first circuit to convey an output voltage during a first cycle of the input clock signal and correct a current mismatch of the first circuit during a second cycle of the input clock signal, the first circuit including a differential pair of transistors for comparing a reference voltage to a voltage across a capacitor configured to receive a first and second current during the second cycle; anda second circuit to convey the output voltage during the second cycle and correct a current mismatch of the second circuit during the first cycle; and a clock generator for receiving the corrected clock signal and generating an output clock.