Glitch Free Clock Frequency Change

摘要

A clock generation circuit generates clock signals of a requested frequency and relative phase by dividing a reference clock signal by counting reference clock signal pulses in a counter circuit. The clock generation circuit changes the frequency, and optionally also the phase, of an output clock signal upon request, without generating glitches or missing pulses. The clock generation circuit does not alter the frequency of the output clock signal until a phase pulse associated with the requested phase is asserted, and the counter circuit is in a predetermined state, such as a reset state.

主权项

1. A synchronous method of changing the frequency, and optionally the phase, of a first clock signal, without introducing transients, comprising:
receiving a reference clock signal; cyclically generating two or more mutually exclusive phase pulses from the reference clock signal, the phase pulses having a predetermined phase relationship to each other; generating an output clock signal of a first frequency by dividing the reference clock signal by a first factor, by cyclically counting a corresponding first number of reference clock pulses; receiving information specifying a requested frequency and phase; and synchronously changing the frequency of the output clock signal according to the received information, only upon the conditions of an asserted value of a phase pulse corresponding to the requested phase and that the reference clock pulse count is in a predetermined state.