| 摘要 |
A solid-state imaging apparatus, wherein an analog to digital conversion unit converts an analog signal from the pixel, a first memory holds the digital signal from the analog to digital conversion unit, and thereafter, a second memory holds the digital signal held by the first memory. The analog to digital conversion unit converts an analog signal from the pixel based on a photoelectric conversion of the pixel, and the first memory holds the digital signal from the analog to digital conversion unit. The first memory includes a first latch circuit holding a digital signal from the analog to digital conversion unit and a second latch circuit holding a signal held by the first latch circuit. The second memory includes a third latch circuit holding a signal held in the first latch circuit and a fourth latch circuit holding a signal held in the third latch circuit. |
| 主权项 |
1. A solid-state imaging apparatus comprising:
a pixel; an analog to digital conversion unit configured to convert an analog signal outputted from the pixel into a digital signal; a first memory; and a second memory, wherein, during a first conversion period, the analog to digital conversion unit converts, to the digital signal, the analog signal outputted from the pixel in response to a reset of the pixel, the first memory holds the digital signal outputted from the analog to digital conversion unit, thereafter, according to the first transfer control signal, the second memory holds the digital signal held by the first memory, during a second conversion period, the analog to digital conversion unit converts, to the digital signal, the analog signal outputted from the pixel based on a photoelectric conversion of the pixel, the first memory holds the digital signal outputted from the analog to digital conversion unit, and wherein the first memory has a first latch circuit configured to hold the digital signal outputted from the analog to digital conversion unit, and a second latch circuit configured to hold the digital signal held by the first latch circuit, according to a second transfer control signal, and the second memory has a third latch circuit configured to hold the digital signal held in the first latch circuit, according to the first transfer control signal, and a fourth latch circuit configured to hold the digital signal held by the third latch circuit, according to a third transfer control signal. |
