发明名称 INTERCONNECT STRUCTURES FOR MINIMIZING CLOCK AND OUTPUT TIMING SKEWS IN A HIGH SPEED CURRENT STEERING DAC
摘要 A digital-to-analog converter (DAC) system includes a DAC and a clock interconnect module. The DAC includes a plurality of segments and a plurality of drivers. Each of the plurality of segments receives driver signals from a respective one of the plurality of drivers and generates a positive output and a negative output based on the driver signals. Each of the plurality of drivers receives a respective one of a plurality of clock signals and outputs the driver signals based on the respective one of the plurality of clock signals. The clock interconnect module includes an interconnect loop. A clock input is connected to a first portion of the interconnect loop and the plurality of clock signals are output from a second portion of the interconnect loop connected to the plurality of drivers. An output interconnect module receives the positive outputs and the negative outputs generates a differential output signal.
申请公布号 US2015244384(A1) 申请公布日期 2015.08.27
申请号 US201514593697 申请日期 2015.01.09
申请人 Maxim Integrated Products, Inc. 发明人 Teterwak Jerzy;McMahill Dan
分类号 H03M1/06;H03M1/66 主分类号 H03M1/06
代理机构 代理人
主权项 1. A digital-to-analog converter (DAC) system comprising: a DAC including a plurality of segments and a plurality of drivers, wherein each of the plurality of segments receives driver signals from a respective one of the plurality of drivers and generates a positive output and a negative output based on the driver signals, and wherein each of the plurality of drivers receives a respective one of a plurality of clock signals and outputs the driver signals based on the respective one of the plurality of clock signals; and a clock interconnect module including an interconnect loop, wherein a clock input is connected to a first portion of the interconnect loop, and wherein the plurality of clock signals are output from a second portion of the interconnect loop connected to the plurality of drivers.
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