| 发明名称 |
METHOD OF TESTING A THREE-DIMENSIONAL INTEGRATED CIRCUIT |
| 摘要 |
A method of testing a three-dimensional integrated circuit (3DIC) includes applying a voltage through at least one testing element and at least one conductive line, wherein the at least one conductive line traces a perimeter of at least one of a top chip or an interposer substantially parallel to an outer edge of the at least one top chip or the interposer, and the at least one conductive line is configured to electrically connect a plurality of conductive connectors. The method further includes measuring a current responsive to the applied voltage. The method further includes determining an integrity of the 3DIC based on the measured current. |
| 申请公布号 |
US2015234004(A1) |
申请公布日期 |
2015.08.20 |
| 申请号 |
US201514700822 |
申请日期 |
2015.04.30 |
| 申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
CHEN Ching-Fang;LU Hsiang-Tai;LIN Chih-Hsien |
| 分类号 |
G01R31/28 |
主分类号 |
G01R31/28 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method of testing a three-dimensional integrated circuit (3DIC), the method comprising:
applying a voltage through at least one testing element and at least one conductive line, wherein the at least one conductive line traces a perimeter of at least one of a top chip or an interposer parallel to an outer edge of the at least one top chip or the interposer, and the at least one conductive line is configured to electrically connect a plurality of conductive connectors; measuring a current responsive to the applied voltage; and determining an integrity of the 3DIC based on the measured current. |
| 地址 |
Hsinchu TW |
