发明名称 Apparatus and method for rapid fuse bank access in a multi-core processor
摘要 <p>An apparatus includes a fuse array, a random access memory (RAM), and a plurality of cores. The fuse array is disposed on a die, where the fuse array has a plurality of semiconductor fuses programmed with compressed configuration data. The RAM is disposed separately on the die. The plurality of cores is disposed separately on the die, where each of the plurality of cores is coupled to the fuse array and the RAM, and where the each of the plurality of cores accesses either the fuse array or the RAM upon power-up/reset as indicated by contents of a load data register to obtain the compressed configuration data.</p>
申请公布号 EP2840510(A3) 申请公布日期 2015.08.19
申请号 EP20130193569 申请日期 2013.11.19
申请人 VIA TECHNOLOGIES, INC. 发明人 HENRY, G GLENN;JAIN, DINESH K.
分类号 G06F15/78;G06F9/445;G11C17/16 主分类号 G06F15/78
代理机构 代理人
主权项
地址