Request-command encoding for reduced-data-rate testing

摘要

Embodiments of a memory device are described. This memory device includes a signal connector which is electrically coupled to a command/address (CA) link, and an interface circuit, which is electrically coupled to the signal connector, and which receives CA packets via the CA link. A given CA packet includes an address field having address information corresponding to one or more storage locations in the memory device. Moreover, the memory device includes control logic having two operating modes, where, during a first operating mode, the control logic decodes address information in the CA packets using full-field sampling, and, during the second operating mode, the control logic decodes a portion of the address information in the CA packets using sub-field sampling.

主权项

1. A memory device, comprising:
a signal connector to electrically couple to a command/address (CA) link; an interface circuit, electrically coupled to the signal connector, to receive CA packets via the CA link, each CA packet including N CA bits, where N is an integer greater than 1; a receiver having two operating modes, wherein, during a first operating mode, the receiver samples each of the N CA bits at respective sample times using full-field sampling, at a first sampling rate, and, during the second operating mode, the receiver samples only a subset of the N bits at selected sample times using sub-field sampling, at a second sampling rate that is less than the first sampling rate; and storage having storage cells that, in the first operating mode, are accessed via an address defined by the sampled N CA bits, and in the second operating mode, are accessed via a portion of a partial address defined by the subset of the N CA bits.