发明名称 Method of forming split-gate cell for non-volative memory devices
摘要 Fabrication of a slim split gate cell and the resulting device are disclosed. Embodiments include forming a first gate on a substrate, the first gate having an upper surface and a hard-mask covering the upper surface, forming an interpoly isolation layer on side surfaces of the first gate and the hard-mask, forming a second gate on one side of the first gate, with an uppermost point of the second gate below the upper surface of the first gate, removing the hard-mask, forming spacers on exposed vertical surfaces, and forming a salicide on exposed surfaces of the first and second gates.
申请公布号 US9111866(B2) 申请公布日期 2015.08.18
申请号 US201313788174 申请日期 2013.03.07
申请人 GLOBALFOUNDRIES SINGAPORE PTE. LTD. 发明人 Chen Yu;Liu Huajun;Chwa Siow Lee;Siah Soh Yun;Shao Yanxia;Lim Yoke Leng
分类号 H01L29/788;H01L21/28;H01L27/115;H01L29/423 主分类号 H01L29/788
代理机构 Ditthavong & Steiner, P.C. 代理人 Ditthavong & Steiner, P.C.
主权项 1. A method comprising: forming a first gate on a substrate, the first gate having an upper surface and a nitride hard-mask covering, and directly contacting, the upper surface; forming an interpoly oxide layer or charge storage layer on side surfaces of the first gate and the nitride hard-mask; depositing a blanket polysilicon layer; etching the blanket polysilicon layer to form a polysilicon spacer with an uppermost point of the polysilicon spacer below the upper surface of the first gate on each side of the first gate; removing the polysilicon spacer from a first side of the first gate, the remaining polysilicon spacer forming a second gate on a second side of the first gate opposite to the first side; removing the nitride hard-mask; forming spacers on all exposed vertical surfaces; and forming a salicide on exposed surfaces of the first and second gates, wherein the first gate is one of a select gate and a control gate, and the second gate is the other of a select gate and a control gate, wherein an uppermost point of the interpoly oxide layer or charge storage layer on the first side is lower than an uppermost point of the second side and an uppermost point of the first gate is lower than the uppermost point of the interpoly oxide layer or charge storage layer on the first side.
地址 Singapore SG
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