发明名称 FAILURE DIAGNOSIS CIRCUIT
摘要 A failure diagnosis circuit includes a multiplexer and a controller. The multiplexer receives address signals, and selectively outputs one of the address signals to an addressable module in response to a selecting signal. The controller generates a first one of address signals and the selecting signal. A built-in self-test circuit generates the second address signal. The addressable module includes addressable components responsive to the address signal. The controller processes the output of the addressable module responsive to the address signal to make a failure diagnosis. The built-in self-test circuit performs signature analysis on the read out output of the addressable module.
申请公布号 US2015228359(A1) 申请公布日期 2015.08.13
申请号 US201514695110 申请日期 2015.04.24
申请人 STMicroelectronics S.r.l. ;STMicroelectronics (Shenzhen) R&D Co. Ltd 发明人 Molinari Luca;Wang Hong Wei
分类号 G11C29/18;G11C8/00;G11C7/00 主分类号 G11C29/18
代理机构 代理人
主权项 1. A method, comprising: supplying a first sequence of address signals to a multiplexer, wherein the first sequence of address signals are configured to test for failure of an addressable circuit and comprise an address value on the addressable circuit; supplying a select signal and a second sequence of address signals to a multiplexer, wherein the second sequence of address signals are configured to test for failure of the addressable circuit and comprise an address value on the addressable circuit; and outputting the first or second sequence of address signals from the multiplexer based upon the select signal.
地址 Agrate Brianza IT