| 摘要 |
In one embodiment, a power management integrated circuit comprises a finite state machine having a first terminal to receive a digital command signal, a second terminal to receive a clock signal, and a third terminal to receive a first reset signal to reset the finite state machine into a predetermined operational state. A plurality of diagnostic registers is configured to store a signal state of the digital command signal or a clock state of the clock signal, or both in response to the first reset signal. The diagnostic registers are configured to maintain the signal state or the clock state, or both after powering down of the power management integrated circuit in response to the first reset signal. The diagnostic registers are configured to allow retrieval of the stored signal state or the stored clock state, or both upon power on of the power management integrated circuit. |
