发明名称 スイッチトキャパシタ回路
摘要 <p>PROBLEM TO BE SOLVED: To provide a switched capacitor circuit that accommodates conversion under a low supply voltage or high speed conversion by significantly suppressing a level variation of an input common voltage to an operational amplifier.SOLUTION: In a switched capacitor circuit 10 for sampling an input signal Vip relative to a reference voltage VIC1 in capacitors C during a sampling period and amplifying the signal sampled in the capacitors C with an operational amplifier A1 during a holding period, the reference voltage VIC1 is a voltage that is the sum of a voltage VIC within an analog common voltage range allowable for the operational amplifier A1 and a differential voltage proportional to a difference between an input common voltage Vci of the input signal and an analog common voltage Vcm.</p>
申请公布号 JP5763112(B2) 申请公布日期 2015.08.12
申请号 JP20130029822 申请日期 2013.02.19
申请人 发明人
分类号 H03F3/45 主分类号 H03F3/45
代理机构 代理人
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