发明名称 Predict computing platform memory power utilization
摘要 A method to reduce memory power consumption for a computing platform includes inspecting an operating parameter associated with a resource of the computing platform that is updated by the resource of the computing platform during runtime of the computing platform. Memory power utilization is then predicted for the computing platform during the runtime of the computing platform based at least in part on the operating parameter. A current power state of at least one memory module resident on the computing platform is transitioned to one of a plurality of power states based on the predicting of the memory power utilization.
申请公布号 US9104409(B2) 申请公布日期 2015.08.11
申请号 US201012752955 申请日期 2010.04.01
申请人 Intel Corporation 发明人 Dodeja Rakesh;Chandwani Neelam;Hiremath Chetan;Mukherjee Udayan;Ambrose Anthony
分类号 G06F1/00;G06F1/32 主分类号 G06F1/00
代理机构 Blakely, Sokoloff, Taylor & Zafman LLP 代理人 Blakely, Sokoloff, Taylor & Zafman LLP
主权项 1. A method to reduce memory power consumption for a computing platform, the method comprising: during runtime of the computing platform, inspecting an operating parameter associated with a resource of the computing platform that is updated by the resource of the computing platform during the runtime of the computing platform; predicting a change from a current level of memory power utilization by the computing platform to another level of memory power utilization by the computing platform during the runtime of the computing platform, the predicting including evaluating, based on the inspecting the operating parameter, a statistical parameter of a statistical prediction algorithm, wherein the operating parameter includes a network traffic parameter, a processing element memory allocation parameter or a memory access pattern parameter; and transitioning a current power state of at least one memory module resident on the computing platform to one of a plurality of power states based on the predicting of the change from the current level of memory power utilization.
地址 Santa Clara CA US