Method and apparatus for synchronization

摘要

Aspects of the disclosure provide a circuit that includes a clock synchronization circuit. The clock synchronization circuit is configured to determine a sub-cycle offset between a first clock signal and a second clock signal, and select rising/failing edges of the first clock signal and the second clock signal based on the sub-cycle offset for enabling communication between a first clock domain that is operative in response to the first clock signal and a second clock domain that is operative in response to the second clock signal.

主权项

1. A circuit, comprising:
a clock synchronization circuit configured to determine a sub-cycle offset between a first clock signal and a second clock signal, and select rising/failing edges of the first clock signal and the second clock signal based on the sub-cycle offset for enabling bi-directional communication between a first clock domain that is operative in response to the first clock signal and a second clock domain that is operative in response to the second clock signal, wherein the clock synchronization circuit comprises:
a sub-cycle offset determination circuit configured to determine an offset in a cycle between the first clock signal and the second clock signal as a number of delay units; anda clock control circuit configured to select the edges of the first clock signal and the second clock signal based on the determined offset.