| 发明名称 |
STREAMING, AT-SPEED DEBUG AND VALIDATION ARCHITECTURE |
| 摘要 |
This application discloses a computing system implementing tools and mechanisms that can incorporate a validation system into a circuit design. The validation system can be configured to monitor at least a portion of an electronic device described in the circuit design. The tools and mechanisms can identify one or more trace signals associated with the electronic device to route to the validation system, and identify one or more trigger signals associated with the electronic device to route to the validation system. The tools and mechanisms can configure the validation system to detect a conditional event corresponding a state of the one or more trigger signals, and to transmit the trace signals associated with the electronic device for debugging in response to the detected conditional event. |
| 申请公布号 |
US2015220677(A1) |
申请公布日期 |
2015.08.06 |
| 申请号 |
US201414473914 |
申请日期 |
2014.08.29 |
| 申请人 |
Mentor Graphics Corporation |
发明人 |
Sehgal Rajeev;Mandavilli Srinivas;Mathews Pradish;Singh Ajit;Potts Henry |
| 分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method comprising:
incorporating, by a computing system, a validation system into a circuit design, wherein the validation system is configured to monitor at least a portion of an electronic device described in the circuit design; identifying, by the computing system, one or more trace signals associated with the electronic device to route to the validation system; and configuring, by the computing system, the validation system to detect a conditional event corresponding to operation of the electronic device, and to transmit the trace signals associated with the electronic device for debugging in response to the detected conditional event. |
| 地址 |
Wilsonville OR US |
