发明名称 |
METHOD AND APPARATUS FOR MODELLING POWER CONSUMPTION OF INTEGRATED CIRCUIT |
摘要 |
A method of modeling power consumption of an integrated circuit and an apparatus for supporting the same are provided. The method of modeling power consumption of an integrated circuit includes: grasping information about a clock gating enable signal of the integrated circuit; determining a modeling level using a change rate of the number of the clock enable signal; and extracting a power state according to the modeling level and the number of the clock gating enable signal and modeling power consumption in the power state. Thereby, because a power state can be defined with only the number of a clock gating enable signal, a dynamic power consumption amount can be quickly and accurately estimated. |
申请公布号 |
US2015220672(A1) |
申请公布日期 |
2015.08.06 |
申请号 |
US201314420303 |
申请日期 |
2013.08.08 |
申请人 |
Samsung Electronics Co., Ltd. |
发明人 |
Park Jihwan |
分类号 |
G06F17/50;G06F17/10 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
1. A method to model power consumption of an integrated circuit, the method comprising:
obtaining information about a clock gating enable signal of the integrated circuit; determining a modeling level using a change rate of a number of the clock gating enable signal; extracting a power state according to the modeling level and the number of the clock gating enable signal; and modeling power consumption in the power state. |
地址 |
Gyeonggi-do KR |