| 发明名称 |
LOW POWER SQUELCH CIRCUIT |
| 摘要 |
Described herein is a low power squelch circuit which comprises a clock generation unit to generate first and second phases of a clock signal; a sampling unit to sample a differential input signal according to the first and second phases of the clock signal, the sampler to generate a sampled differential signal; and a differential amplifier to amplify the sampled differential signal. |
| 申请公布号 |
US2015222417(A1) |
申请公布日期 |
2015.08.06 |
| 申请号 |
US201113994096 |
申请日期 |
2011.12.21 |
| 申请人 |
Song Hongjiang;Le Dianbo |
发明人 |
Song Hongjiang;Le Dianbo |
| 分类号 |
H04L7/00;H04L7/10 |
主分类号 |
H04L7/00 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An apparatus comprising:
a clock generation unit to generate first and second phases of a clock signal; a sampling unit to sample a differential input signal according to the first and second phases of the clock signal, the sampler to generate a sampled differential signal; and a differential amplifier to amplify the sampled differential signal. |
| 地址 |
Mesa AZ US |
