| 发明名称 |
AREA EFFICIENT MULTIPORT BITCELL |
| 摘要 |
A multiport bitcell apparatus includes a plurality of word lines for enabling writing and reading operations. The word lines include a first set of word lines extending across the bitcell on a first metal layer. The word lines further include a second set of word lines extending across the bitcell on a second metal layer. The word lines further include a third set of word lines extending across the bitcell on both the first metal layer and the second metal layer. The third set of word lines may include a first word line that extends on a first metal track and a second metal track, and a second word line that extends on the second metal track and a third metal track. The first metal layer may be an M2 layer and the second metal layer may be an M3 layer. |
| 申请公布号 |
US2015221346(A1) |
申请公布日期 |
2015.08.06 |
| 申请号 |
US201414173788 |
申请日期 |
2014.02.05 |
| 申请人 |
QUALCOMM Incorporated |
发明人 |
VATTIKONDA Rakesh;NGURE Frederick;JUNG Changho |
| 分类号 |
G11C5/02;G11C7/00 |
主分类号 |
G11C5/02 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A multiport bitcell apparatus including a plurality of word lines for enabling writing and reading operations, the word lines comprising:
a first set of word lines extending across the bitcell on a first metal layer; a second set of word lines extending across the bitcell on a second metal layer; and a third set of word lines extending across the bitcell on both the first metal layer and the second metal layer. |
| 地址 |
San Diego CA US |
