Self-aligned structures and methods for asymmetric GaN transistors and enhancement mode operation

摘要

Embodiments include high electron mobility transistors (HEMT). In embodiments, a gate electrode is spaced apart by different distances from a source and drain semiconductor region to provide high breakdown voltage and low on-state resistance. In embodiments, self-alignment techniques are applied to form a dielectric liner in trenches and over an intervening mandrel to independently define a gate length, gate-source length, and gate-drain length with a single masking operation. In embodiments, III-N HEMTs include fluorine doped semiconductor barrier layers for threshold voltage tuning and/or enhancement mode operation.

主权项

1. A high electron mobility field effect transistor (HEMT), comprising:
a group III-N semiconductor channel layer disposed over a substrate; a gate stack disposed over a first region of the channel layer; a source region in contact with the channel layer on a first side of the gate stack; a drain region in contact with the channel layer on a second side of the gate stack opposite the source region; a dielectric liner disposed over a first length of a semiconductor barrier layer between the source region and the gate stack, and disposed over a second length of the semiconductor barrier layer between the drain region and the gate stack that is larger than the first length, wherein the dielectric liner comprises first liner sidewalls on opposite sides of the gate stack, and further comprises a second liner sidewall defining the first or second length with a filler dielectric disposed between the first liner sidewalls and the second liner sidewall.