Chip stack device testing method, chip stack device rearranging unit, and chip stack device testing apparatus

摘要

A plurality of chip stack devices having different external sizes can be tested accurately and efficiently with low cost. The present invention provides a chip stack device testing method testing a chip stack device configured by stacking a plurality of chips separated by dicing a substrate under test tested in a testing unit. A tray for chip stack devices having equal shape and external dimension to those of the undiced substrate under test is used, one or a plurality of the chip stack devices are attached and supported to an adhesive layer of the tray for chip stack devices to align the chip stack devices with positions of the respective chips of the undiced substrate under test, the tray for chip stack devices is installed in the testing unit in a similar manner to that in a test of the substrate under test, and the respective chip stack devices are tested.

主权项

1. A chip stack device testing method for testing a chip stack device, said chip stack device being configured by stacking a plurality of chips, and said plurality of chips having been separated by dicing an undiced substrate under test tested in a testing unit by using the testing unit testing the substrate under test, comprising:
using a tray for chip stack devices, said tray having equal shape and external dimension to those of the undiced substrate under test and having an adhesive layer on a surface and placing therein chip stack devices configured by stacking a plurality of chips separated by the dicing; attaching and supporting one or a plurality of the chip stack devices which are configured by stacking a plurality of chips separated by the dicing to the adhesive layer of the tray for chip stack devices to align the chip stack devices with positions originally arranged of the respective chips of the undiced substrate under test; and installing the tray for chip stack devices in the testing unit having done the test of the substrate under test in a similar manner to that in a test of the undiced substrate under test and testing the respective chip stack devices attached to the adhesive layer in a similar manner to that in a test of the substrate under test.