Non-volatile static ram cell circuit and timing method

摘要

A non-volatile static random access memory cell and includes a bistable regenerative circuit coupled to first and second transistors and to first and second non-volatile memory cells. Methods of use include directly transferring a complementary data bit between the non-volatile memory cell and the bistable regenerative circuit. Alternatively, complementary data from the bistable regenerative circuit may be regenerated by a sense amplifier and a second bistable regenerative circuit before being transferred to non-volatile memory cells in a column of memory cells. The bistable regenerative circuit may be reset to ground potential. Applications using the non-volatile SRAM cell with direct read out from the bistable regenerative circuit include a non-volatile flip-flop or non-volatile multiplexer.

主权项

1. A non-volatile static random access memory cell, comprising:
a bistable regenerative circuit; a first transistor comprising a first current carrying terminal coupled to a first terminal of said bistable regenerative circuit, and a second current carrying terminal coupled to a first signal line; a second transistor comprising a first current carrying terminal coupled to a second terminal of said bistable regenerative circuit, and a second current carrying terminal coupled to a second signal line; a first non-volatile memory cell comprising a first current carrying terminal coupled to said first terminal of said bistable regenerative circuit, a second current carrying terminal coupled to said first signal line, a first magnetic tunnel junction comprising a first terminal coupled to a second current carrying terminal of said first non-volatile memory cell, and a third transistor comprising a first current carrying terminal, a gate terminal and a second current carrying terminal, the first current carrying terminal of the third transistor being coupled to said first current carrying terminal of said first non-volatile memory cell, the gate terminal of the third transistor being coupled to a control terminal of said first non-volatile memory cell and the second current carrying terminal of the third transistor being coupled to a second terminal of said first magnetic tunnel junction; and a second non-volatile memory cell comprising a first current carrying terminal coupled to said second terminal of said bistable regenerative circuit, a second current carrying terminal coupled to said second signal line, a second magnetic tunnel junction comprising a first terminal coupled to a second current carrying terminal of said second non-volatile memory cell, and a fourth transistor comprising a first current carrying terminal, a gate terminal and a second current carrying terminal, the first current carrying terminal of the fourth transistor being coupled to said first current carrying terminal of said second non-volatile memory cell, the gate terminal of the fourth transistor being coupled to a control terminal of said second non-volatile memory cell and the second current carrying terminal of the fourth transistor being coupled to a second terminal of said second magnetic tunnel junction, wherein the control terminals of said first and second non-volatile memory cells are coupled to a third signal line and gate terminals of said first and second transistors are coupled to a fourth signal line.