| 摘要 |
An information processor includes an information processing sub-system having information processing circuits and a memory sub-system performing data communication with the information processing sub-systems, wherein the memory sub-system has a first memory, a second memory, a third memory having reading and writing latencies longer than those of the first memory and the second memory, and a memory controller for controlling data transfer among the first memory, the second memory and the third memory; graph data is stored in the third memory; the memory controller analyzes data blocks serving as part of the graph data, and performs preloading operation repeatedly to transfer the data blocks to be required next for the execution of the processing from the third memory to the first memory or the second memory on the basis of the result of the analysis. |
| 主权项 |
1. An information processor comprising:
an information processing sub-system; and a memory sub-system performing data communication with the information processing sub-system, wherein the information processing sub-system has an information processing circuit for processing a graph according to graph processing instructions, the memory sub-system has a first memory, a second memory, a third memory having reading and writing latencies longer than those of the first memory and the second memory, and a memory controller for controlling data transfer among the first memory, the second memory and the third memory, in graph data to be subjected to the processing of the graph, to each of the vertices of the graph, an ID for uniquely specifying each of the vertices is assigned, and in the case that the ID assigned to one of the vertices is known, it is possible to specify where the IDs of other vertices relating to the vertex are located in an address space, and the graph data has a plurality of data blocks, the data block is all data or part of the data corresponding to an address identified by analyzing the ID of the one vertex using the memory controller, and at least the ID of the one vertex is recorded therein, the memory controller has a function of storing the graph data to be processed into the third memory and a preloading function of transferring the plurality of data blocks from the third memory to the first memory or the second memory, by using the preloading function, the memory controller autonomously analyzes the ID of at least one vertex included in one data block A of the data blocks, calculates the address of at least one data block B to be required next by the information processing circuit, and transfers the data block B from the third memory to the first memory or the second memory, and then analyzes the ID of at least one vertex included in the data block A or block B transferred previously from the third memory to the first memory or the second memory or included in a data block C different from the data blocks A and B, calculates the address of at least one data block D to be required next by the information processing circuit, and transfers the data block D from the third memory to the first memory or the second memory, and then similarly transfers a plurality of data blocks from the third memory to the first memory or the second memory, and the information processing circuit reads out the graph data from the first memory or the second memory different from the transfer destination of the data block in which the preloading function is being executed, and executes the processing of the graph data according to the processing instructions. |
