发明名称 |
Method and apparatus for circuit emulation with integrated network diagnostics and reduced form factor in large public communication networks |
摘要 |
An multiservice access device (MAD) for Ethernet and DS1/DS3 services is provided for public communications carriers (telcos), for example, and has a reduced form factor (e.g., Type 400 NCTE mechanics or small enclosure), at least two 2.5 Gb/1 Gb facility side ports, at least four full rate GigE drops, complementary RJ48C demarcation and stub-ended DS1 cable options, integral T1 NIUs for in-band loopback, NPRM, SPRM, AIS/AIS-CI and RAI/RAI-CI diagnostics, lightning protection, and protection switching. The MAD has built-in SynchE and IEEE 1588 synchronization, and Stratum 3 and incoming DS1/DS3 synchronization capabilities. |
申请公布号 |
US9100208(B2) |
申请公布日期 |
2015.08.04 |
申请号 |
US201113283069 |
申请日期 |
2011.10.27 |
申请人 |
HUBBELL INCORPORATED |
发明人 |
Schmitz Peter Bradley;Corp David Owen;Ramsay Natalie C. |
分类号 |
H04L12/40;H04J3/04;H04J3/06 |
主分类号 |
H04L12/40 |
代理机构 |
Roylance, Abrams, Berdo & Goodman, L.L.P. |
代理人 |
Roylance, Abrams, Berdo & Goodman, L.L.P. |
主权项 |
1. A multiservice access device, comprising:
a synchronous network receiver for receiving synchronous network traffic; a plurality of network interface debuggers integral to the multiservice access device for generating messages related to the status of the synchronous network; a packet processor for processing the synchronous network traffic and messages into packetized synchronous network data for asynchronous transmission over an Ethernet network in a first bus format; a first bus translator for translating the first bus format into a second bus format; an Ethernet processor for receiving the packetized synchronous network data in the second bus format and asynchronously transmitting the packetized synchronous network data over Ethernet; a clock synchronizing device for receiving clock information from a plurality of devices and status information from the synchronous network receiver, the network interface debuggers, and the packet processor and determining a clock, and providing the clock to the synchronous network receiver, the network interface debuggers, and the packet processor; and a processor for managing the operation of the transceiver, the packet processor, and the Ethernet processor, wherein the processor sends and receives control information from the Ethernet processor on a third bus interface. |
地址 |
Shelton CT US |