METHODS FOR FABRICATING FINFET INTEGRATED CIRCUITS WITH SIMULTANEOUS FORMATION OF LOCAL CONTACT OPENINGS

摘要

A method for fabricating a finFET integrated circuit includes providing a finFET integrated circuit structure including a fin structure, a replacement metal gate structure having a silicon nitride cap disposed over and in contact with the fin structure, a contact structure including a tungsten material also disposed over and in contact with the fin structure, and an insulating layer disposed over the replacement metal gate structure and the contact structure. The method further includes forming a first opening in the insulating layer over the replacement gate structure and a second opening in the insulating layer over the contact structure. Forming the first and second openings includes exposing the FinFET integrated circuit structure to a single extreme ultraviolet lithography patterning. Still further, the method includes removing a portion of the silicon nitride material of the replacement metal gate structure and forming a metal fill material in the first and second openings.

主权项

1. A method for fabricating a finFET integrated circuit comprising:
forming a fin structure on a semiconductor substrate; forming a gate electrode structure over the fin structure; forming a silicon nitride capping layer over the gate electrode structure; forming a TS contact plug over the fin structure and adjacent to the gate electrode structure, wherein the TS contact plug is formed such that a top surface thereof is coplanar with a top surface of the silicon nitride capping layer over the gate electrode structure; forming a low-k insulating layer over the silicon nitride capping layer and over the TS contact plug; forming at least two openings in the low-k insulating layer, wherein a first opening of the at least two openings exposes the top surface of the silicon nitride capping layer, and wherein a second opening of the at least two openings exposes the top surface of the TS contact plug, and wherein the step of forming the at least two openings is performed using a single etching step; extending the first opening to form an extended first opening that extends the first opening to the gate electrode structure while not extending the second opening; and depositing a conducting material in the extended first opening and the second opening to form contacts to the gate electrode and to the TS contact plug.