发明名称 Group III-N transistors on nanoscale template structures
摘要 A III-N semiconductor channel is formed on a III-N transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall. In embodiments, the silicon fin has a width comparable to the III-N epitaxial film thicknesses for a more compliant seeding layer, permitting lower defect density and/or reduced epitaxial film thickness. In embodiments, a transition layer is GaN and the semiconductor channel comprises Indium (In) to increase a conduction band offset from the silicon fin. In other embodiments, the fin is sacrificial and either removed or oxidized, or otherwise converted into a dielectric structure during transistor fabrication. In certain embodiments employing a sacrificial fin, the III-N transition layer and semiconductor channel is substantially pure GaN, permitting a breakdown voltage higher than would be sustainable in the presence of the silicon fin.
申请公布号 GB201510569(D0) 申请公布日期 2015.07.29
申请号 GB20150010569 申请日期 2013.06.24
申请人 INTEL CORPORATION 发明人
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