Systems and methods for reducing branch misprediction penalty

摘要

In a processing system capable of single and multi-thread execution, a branch prediction unit can be configured to detect hard to predict branches and loop instructions. In a dual-threading (simultaneous multi-threading) configuration, one instruction queues (IQ) is used for each thread and instructions are alternately sent from each IQ to decode units. In single thread mode, the second IQ can be used to store the “not predicted path” of the hard-to-predict branch or the “fall-through” path of the loop. On mis-prediction, the mis-prediction penalty is reduced by getting the instructions from IQ instead of instruction cache.

主权项

1. In a data processing system having an instruction fetch unit, a decode unit, and a branch execution unit, the instruction fetch unit being coupled to a branch target buffer (BTB), and having a first instruction queue for providing instructions to the decode unit, and a second instruction queue for providing instructions to the decode unit, the decode unit issuing instructions for execution, a method comprising:
in single thread mode:
providing a first instruction address to the instruction fetch unit;fetching a first instruction from the first instruction address and storing the first instruction in the first instruction queue;determining whether the first instruction address hits in the BTB;in response to determining that the first instruction address hits in the BTB, using an entry in the BTB which resulted in the hit to determine whether the first instruction is a conditional branch and whether it is predicted as a taken branch or a non-taken branch;in response to determining that the first instruction is a conditional branch and predicted as a taken branch:
providing a target address from the entry in the BTB to the instruction fetch unit;fetching a second instruction from the target address and storing the second instruction in the first instruction queue; andfetching one or more sequential instructions which are sequential to the first instruction and storing the one or more sequential instructions in the second instruction queue; andin response to determining that the first instruction is a conditional branch and predicted as a non-taken branch:
providing the target address from the entry in the BTB to the instruction fetch unit;fetching a third instruction fetched from the target address and storing the third instruction in the second instruction queue;providing a sequential address to the first instruction to the instruction fetch unit; andstoring a fourth instruction fetched from the sequential address in the first instruction queue;providing the first instruction from the first instruction queue to the decode unit; andissuing the first instruction from the decode unit for execution, wherein
the branch execution unit resolves the first instruction to determine if the prediction made using the entry in the BTB is correct or mispredicted, andif the first instruction is a conditional branch, providing an identifier with the first instruction to the decode unit and the branch execution unit, wherein the identifier identifies a location in the second instruction queue of one or more instructions which are to be executed if the first instruction is mispredicted.