发明名称 Semiconductor device
摘要 A semiconductor device comprising a substrate in which a first region and a second region are defined, a gate line which extends in a first direction and traverses the first region and the second region, a source region including a portion formed in the first region, a first part of a body region which is formed under the portion of the source region in the first region and has a first width, a first well which is formed under the first part of the body region in the first region and has a second width greater than the first width, a second part of the body region which is formed in the second region and has a third width, and a second well which is formed under the second part of the body region in the second region and has a fourth width smaller than the third width.
申请公布号 US9093472(B2) 申请公布日期 2015.07.28
申请号 US201314014675 申请日期 2013.08.30
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 Kim Min-Hwan
分类号 H01L29/66;H01L29/00;H01L29/78;H01L29/10;H01L29/45;H01L29/06;H01L29/08 主分类号 H01L29/66
代理机构 F. Chau & Associates, Inc. 代理人 F. Chau & Associates, Inc.
主权项 1. A method of fabricating a semiconductor device, the method comprising: forming a P-type well having a first sun P-type well and a plurality of second sub P-type wells in a substrate, wherein the first sub P-type well is continuously extended in a first direction and wherein each pair of the plurality of second sub P-type wells is extended from both sides of the first sub P-type well in a second direction crossing the first direction and is arranged at a regular interval in the first direction; forming a P-type body region having a first region and a second region in the substrate, wherein the P-type body region is extended in the first direction, wherein the first rat region of the P-type body region is formed on the first sub P-type well, wherein the second region of the P-type body region is surrounded by the each pair of the plurality of the second sub P-type wells, and wherein the P-type body region includes a source region and a body contact region; and forming a gate line on the substrate, wherein the gate line is extended in the first direction.
地址 Suwon-Si, Gyeonggi-Do KR