发明名称 | Efficient parallel floating point exception handling in a processor | ||
摘要 | Methods and apparatus are provided for handling floating point exceptions in a processor that executes single-instruction multiple-data (SIMD) instructions. In one example a numerical exception is identified for a SIMD floating point operation and SIMD micro-operations are initiated to generate two packed partial results of a packed result for the SIMD floating point operation. A SIMD denormalization micro-operation is initiated to combine the two packed partial results and to denormalize one or more elements of the combined packed partial results to generate a packed result for the SIMD floating point operation having one or more denormal elements. Flags are set and stored with packed partial results to identify denormal elements. In one example a SIMD normalization micro-operation is initiated to generate a normalized pseudo internal floating point representation prior to the SIMD floating point operation when it uses multiplication. | ||
申请公布号 | US9092226(B2) | 申请公布日期 | 2015.07.28 |
申请号 | US201113325559 | 申请日期 | 2011.12.14 |
申请人 | Intel Corporation | 发明人 | Sperber Zeev;Finkelstein Shachar;Pribush Gregory;Gradstein Amit;Bale Guy;Pons Thierry |
分类号 | G06F9/38;G06F9/30 | 主分类号 | G06F9/38 |
代理机构 | Trop, Pruner & Hu, P.C. | 代理人 | Trop, Pruner & Hu, P.C. |
主权项 | 1. A method comprising: identifying, in a processor, a numerical exception for a single-instruction multiple-data (SIMD) floating point operation; responsive to identifying the numerical exception, initiating, in the processor, a first SIMD micro-operation to generate a first packed partial result for the SIMD floating point operation, without conversion of a first packed source operand and a second packed source operand for the SIMD floating point operation; responsive to identifying the numerical exception, initiating, in the processor, a second SIMD micro-operation to generate a second packed partial result for the SIMD floating point operation, without the conversion; initiating, in the processor, a SIMD denormalization micro-operation to combine the first and second packed partial results and to denormalize a first element of the combined first and second packed partial results to generate a third packed result having a denormal element; storing the third packed result for the SIMD floating point operation; and setting a flag identifying the denormal element of the third packed result in said first packed partial result. | ||
地址 | Santa Clara CA US |