发明名称 BARRIER TRANSACTION IN INTERCONNECTS
摘要 Interconnect circuitry for a data processing apparatus is disclosed. The interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device, said interconnect circuitry comprising: at least one input for receiving transaction requests from said at least one initiator device; at least one output for out-putting transaction requests to said at least one recipient device; at least one path for transmitting said transaction requests be¬tween said at least one input and said at least one output; control circuitry for routing said received transaction requests from said at least one input to said at least one output; wherein said control circuitry is configured to respond to a barrier transaction request to maintain an ordering of at least some transaction requests with respect to said barrier transaction request within a stream of transaction requests passing along one of said at least one paths, by not allowing reordering of at least some transactions requests that occur before said barrier transaction request in said stream of transaction requests with respect to at least some transaction requests that occur after said barrier transaction request in said stream of transaction requests; wherein said barrier transaction request comprising an indicator indicating which of said transaction requests within said stream of transaction requests comprise said at least some transaction requests whose ordering is to be maintained.
申请公布号 IN2792DEN2012(A) 申请公布日期 2015.07.24
申请号 IN2012DELNP2792 申请日期 2012.04.02
申请人 ARM LIMITED 发明人 PETER, ANDREW RIOCREUX;BRUCE, JAMES MATHEWSON;CHRISTOPHER, WILLIAM LAYCOCK;RICHARD, ROY GRISENTHWAITE
分类号 G06F13/16 主分类号 G06F13/16
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