SEMICONDUCTOR CIRCUIT AND METHOD OF OPERATING THE CIRCUIT

摘要

Provided is a semiconductor circuit which includes a first circuit configured to determine a voltage level of a feedback node based on a voltage level of input data, a voltage level of a latch input node, and a voltage level of a clock signal, a second circuit configured to pre-charge the latch input node based on the voltage level of the clock signal, a third circuit configured to pull down the latch input node based on the voltage level of the feedback node and the voltage level of the clock signal, a latch configured to output output data based on the voltage level of the clock signal and the voltage level of the latch input node, and a control circuit included in at least one of the first to third circuits and the latch and configured to receive the control signal.

主权项

1. A semiconductor circuit performing different operations according to a control signal supplied thereto, the semiconductor circuit comprising:
a first circuit configured to determine a voltage level of a feedback node based on a voltage level of input data, a voltage level of a latch input node, and a voltage level of a clock signal; a second circuit configured to pre-charge the latch input node based on the voltage level of the clock signal; a third circuit configured to pull down the latch input node based on the voltage level of the feedback node and the voltage level of the clock signal; a latch configured to output output data based on the voltage level of the clock signal and the voltage level of the latch input node; and a control circuit included in at least one of the first to third circuits and the latch, and configured to receive the control signal, wherein the latch comprises:
a first transistor gated to the voltage level of the latch input node and configured to pull up an output node;a second transistor gated to an inverted voltage level of the feedback node and configured to pull down the output node; anda third transistor connected in series to the second transistor, gated to the voltage level of the clock signal and configured to pull down the output node.