GATE DRIVER ON ARRAY (GOA) CIRCUIT AND DISPLAY PANEL WITH SAME

摘要

The present invention provides a gate driver on array (GOA) circuit and a display panel with the GOA circuit. The driver circuit includes multiple stages of gate driver units and multiple stages of supplementary gate driver units connected in cascade, in which the nth stage gate driver unit includes a driving unit (42) and a pull-down unit (44) and the mth stage supplementary gate driver unit includes a supplementary driving unit (52) and a supplementary pull-down unit (54). The GOA circuit according to the present invention adopts a dual-pull-down architecture so that thin-film transistors contained in pull-down units and supplementary pull-down units of the circuit can be set in an operation environment featuring dual polarity electrical biasing to effectively suppress threshold voltage drifting of the thin-film transistors of the pull-down units and the supplementary pull-down units and extend the lifespan of circuit thereby making the circuit better meet the needs of large- and medium-sized display panels. Further, the circuit has a simple structure and reduced power consumption and is also fit to low temperature and high temperature operations.

主权项

1. A GOA (Gate Drive on Array) circuit, comprising multiple stages of the gate driver units and multiple stages of the supplementary gate driver units connected in cascade, wherein:
a nth stage gate driver unit comprises a (n−2)th signal input terminal, a (n+1)th signal input terminal, a (n+3)th signal input terminal, a high-frequency clock signal first input terminal, a low-frequency clock signal first input terminal, a low-frequency clock signal second input terminal, a low level input terminal, a first output terminal, and a second output terminal, wherein the first output terminal of the nth stage array substrate row driving unit functions to drive a pixel zone of a display panel; a mth stage supplementary gate driver unit comprises a (m−1)th supplementary signal input terminal, a high-frequency clock signal first input terminal, a high-frequency clock signal second input terminal, a low-frequency clock signal first input terminal, a low-frequency clock signal second input terminal, a low level input terminal, a first supplementary output terminal, and a second supplementary output terminal; when the nth stage gate driver unit is one of the fourth stage to the fourth last stage gate driver unit, the (n−2)th signal input terminal of the nth stage gate driver unit is electrically connected to the first output terminal of the (n−2)th stage gate driver unit; the (n+1)th signal input terminal of the nth stage gate driver unit is electrically connected to the second output terminal of the (n+1)th stage gate driver unit; the (n+3)th signal input terminal of the nth stage gate driver unit is electrically connected to the first output terminal of the (n+3)th stage gate driver unit; the first output terminal of the nth stage gate driver unit is electrically connected to the (n−2)th signal input terminal of the (n+2)th stage gate driver unit and the (n+3)th signal input terminal of the (n−3)th stage gate driver unit; and the second output terminal of the nth stage gate driver unit is electrically connected to the (n+1)th signal input terminal of the (n−1)th stage gate driver unit; when the nth stage gate driver unit is the first stage gate driver unit, the (n−2)th signal input terminal of the nth stage gate driver unit functions to receive an input of a pulse excitation signal; the (n+1)th signal input terminal of the nth stage gate driver unit is electrically connected to the second output terminal of the (n+1)th stage gate driver unit; the (n+3)th signal input terminal of the nth stage gate driver unit is electrically connected to the first output terminal of the (n+3)th stage gate driver unit; the first output terminal of the nth stage gate driver unit is electrically connected to the (n−2)th signal input terminal of the (n+2)th stage gate driver unit; and the second output terminal of the nth stage gate driver unit is floating; when the nth stage gate driver unit is the second stage gate driver unit, the (n−2)th signal input terminal of the nth stage gate driver unit functions to receive an input of a pulse excitation signal; the (n−1)th signal input terminal of the nth stage gate driver unit is electrically connected to the second output terminal of the (n+1)th stage gate driver unit; the (n+3)th signal input terminal of the nth stage gate driver unit is electrically connected to the first output terminal of the (n+3)th stage gate driver unit; the first output terminal of the nth stage gate driver unit is electrically connected to the (n−2)th signal input terminal of the (n+2)th stage gate driver unit; and the second output terminal of the nth stage gate driver unit is electrically connected to the (n+1)th signal input terminal of the (n−1)th stage gate driver unit; when the nth stage gate driver unit is the third stage gate driver unit, the (n−2)th signal input terminal of the nth stage gate driver unit is electrically connected to the first output terminal of the (n−2)th stage gate driver unit; the (n+1)th signal input terminal of the nth stage gate driver unit is electrically connected to the second output terminal of the (n−1)th stage gate driver unit; the (n+3)th signal input terminal of the nth stage gate driver unit is electrically connected to the first output terminal of the (n+3)th stage gate driver unit; the first output terminal of the nth stage gate driver unit is electrically connected to the (n−2)th signal input terminal of the (n+2)th stage gate driver unit; and the second output terminal of the nth stage gate driver unit is electrically connected to the (n+1)th signal input terminal of the (n−1)th stage gate driver unit; when the nth stage gate driver unit is the third last stage gate driver unit, the (n−2)th signal input terminal of the nth stage gate driver unit is electrically connected to the first output terminal of the (n−2)th stage gate driver unit; the (n+1)th signal input terminal of the nth stage gate driver unit is electrically connected to the second output terminal of the (n−1)th stage gate driver unit; the (n+3)th signal input terminal of the nth stage gate driver unit is electrically connected to the first supplementary output terminal of the first stage supplementary gate driver unit; the first output terminal of the nth stage gate driver unit is electrically connected to the (n−2)th signal input terminal of the (n+2)th stage gate driver unit and the (n+3)th signal input terminal of the (n−3)th stage gate driver unit; and the second output terminal of the nth stage gate driver unit is electrically connected to the (n+1)th signal input terminal of the (n−1)th stage gate driver unit; when the nth stage gate driver unit is the second last stage gate driver unit, the (n−2)th signal input terminal of the nth stage gate driver unit is electrically connected to the first output terminal of the (n−2)th stage gate driver unit; the (n+1)th signal input terminal of the nth stage gate driver unit is electrically connected to the second output terminal of the (n+1)th stage gate driver unit; the (n+3)th signal input terminal of the nth stage gate driver unit is electrically connected to the first supplementary output terminal of the second stage supplementary gate driver unit; the first output terminal of the nth stage gate driver unit is electrically connected to the (n+3)th signal input terminal of the (n−3)th stage gate driver unit; and the second output terminal of the nth stage gate driver unit is electrically connected to the (n−1)th signal input terminal of the (n−1)th stage gate driver unit; when the nth stage gate driver unit is the last stage gate driver unit, the (n−2)th signal input terminal of the nth stage gate driver unit is electrically connected to the first output terminal of the (n−2)th stage gate driver unit; the (n+1)th signal input terminal of the nth stage gate driver unit is electrically connected to the second supplementary output terminal of the first stage supplementary gate driver unit; the (n+3)th signal input terminal of the nth stage gate driver unit is electrically connected to the first supplementary output terminal of the third stage supplementary gate driver unit; the first output terminal of the nth stage gate driver unit is electrically connected the (n+3)th signal input terminal of the (n−3)th stage gate driver unit and the (m−1)th supplementary signal input terminal of the first stage supplementary gate driver unit; and the second output terminal of the nth stage gate driver unit is electrically connected to the (n+1)th signal input terminal of the (n−1)th stage gate driver unit; when the mth stage supplementary gate driver unit is one of the fourth stage to the last stage supplementary gate driver unit, the (m−1)th supplementary signal input terminal of the mth stage supplementary gate driver unit is electrically connected to the first supplementary output terminal of the (m−1)th stage supplementary gate driver unit; the first supplementary output terminal of the mth stage supplementary gate driver unit is electrically connected to the (m−1)th supplementary signal input terminal of the (m+1)th stage supplementary gate driver unit; and the second supplementary output terminal is floating; when the mth stage supplementary gate driver unit is the first stage supplementary gate driver unit, the (m−1)th supplementary signal input terminal of the mth stage supplementary gate driver unit is electrically connected to the first output terminal of the last stage gate driver unit; the first supplementary output terminal of the mth stage supplementary gate driver unit is electrically connected to the (m−1)th supplementary signal input terminal of the (m+1)th stage supplementary gate driver unit and the (n+3)th signal input terminal of the third last stage gate driver unit; and the second supplementary output terminal is electrically connected to the (n+1)th signal input terminal of the last stage gate driver unit; when the mth stage supplementary gate driver unit is the second stage supplementary gate driver unit, the (m−1)th supplementary signal input terminal of the mth stage supplementary gate driver unit is electrically connected to the first supplementary output terminal of the (m−1)th stage supplementary gate driver unit; the first supplementary output terminal of the mth stage supplementary gate driver unit is electrically connected to the (m−1)th supplementary signal input terminal of the (m+1)th stage supplementary gate driver unit and the (n+3)th signal input terminal of the second last stage gate driver unit; and the second supplementary output terminal is floating; when the mth stage supplementary gate driver unit is the third stage supplementary gate driver unit, the (m−1)th supplementary signal input terminal of the mth stage supplementary gate driver unit is electrically connected to the first supplementary output terminal of the (m−1)th stage supplementary gate driver unit; the first supplementary output terminal of the mth stage supplementary gate driver unit is electrically connected to the (m−1)th supplementary signal input terminal of the (m+1)th stage supplementary gate driver unit and the (n+3)th signal input terminal of the last stage gate driver unit; and the second supplementary output terminal is floating; the nth stage gate driver unit of the GOA circuit further comprises: a driving unit, which is electrically connected to the (n−2)th signal input terminal, the high-frequency clock signal first input terminal, the (n+3)th signal input terminal, the first output terminal, and the second output terminal; and a pull-down unit, which is electrically connected to the (n+1)th signal input terminal, the low-frequency clock signal first input terminal, the low-frequency clock signal second input terminal, the low level input terminal, and the driving unit; the mth stage supplementary gate driver unit of the GOA circuit further comprises: a supplementary driving unit, which is electrically connected to the (m−1)th supplementary signal input terminal, the high-frequency clock signal first input terminal, the high-frequency clock signal second input terminal, the first supplementary output terminal, and the second supplementary output terminal; and a supplementary pull-down unit, which is electrically connected to the low-frequency clock signal first input terminal, the low-frequency clock signal second input terminal, the low level input terminal, and the supplementary driving unit.