System and apparatus for consolidated dynamic frequency/voltage control

摘要

Methods and apparatus for accomplishing dynamic frequency/voltage control between at least two processor cores in a multi-processor device or system include receiving busy, idle and wait, time and/or frequency information from a first processor core and receiving busy, idle, wait, time and/or frequency information from a second processor core. The received busy, idle, wait, time and/or frequency information may be correlated to identify patterns of interdependence. The correlated information may be used to determine dynamic frequency/voltage control settings for the first and second processor cores to provide a performance level that accommodates interdependent processes, threads and processor cores. The correlation of received busy, idle, wait, time and/or frequency information may involve generating a consolidated busy/idle pulse train that can then be used to set the frequency or voltage of each processor core independently.

主权项

1. A method of performing dynamic clock and voltage scaling on a multiprocessor system having two or more processor cores, the method comprising:
receiving a first set of information from a first processor core, the first information set including information regarding at least one of a frequency, time, busy periods, idle periods and wait periods of the first processor core; receiving a second set of information from a second processor core, the second information set including information regarding at least one of a frequency, time, busy periods, idle periods and wait periods of the second processor core; synchronizing the first and second information sets; correlating the synchronized first and second information sets to identify an interdependence relationship between operations of the first processor core and operations of the second processor core; and scaling the frequency or a voltage of the first processor core and scaling the frequency or a voltage of the second processor core according to a correlated information set when an interdependence relationship is identified between the operations of the first processor core and the operations of the second processor core, wherein scaling the frequency or the voltage of the first processor core and scaling the frequency or the voltage of the second processor core according to the correlated information set comprises:
determining an appropriate frequency or voltage for the first processor core and an appropriate frequency or voltage for the second processor core according to the correlated information set; andadjusting the frequency or the voltage of the first processor core and the frequency or the voltage of the second processor core based on the determined appropriate frequency or voltage for the first processor core and the determined appropriate frequency or voltage for the second processor core.