Power napping technique for accelerated negative bias temperature instability (NBTI) and/or positive bias temperature instability (PBTI) recovery

摘要

A logic circuit is operated in a normal mode, with a supply voltage coupled to a supply rail of the logic circuit, and with a ground rail of the logic circuit grounded; It is determined that at least a portion of the logic circuit has experienced degradation due to bias temperature instability. Responsive to the determining, the logic circuit is operated in a power napping mode, with the supply voltage coupled to the ground rail of the circuit, with the supply rail of the circuit grounded, and with primary inputs of the circuit toggled between logical zero and logical one at low frequency. A logic circuit and corresponding design structures are also provided.

主权项

1. A method comprising the steps of:
operating a logic circuit in a normal mode, with a supply voltage coupled to a supply rail of said logic circuit, and with a ground rail of said logic circuit grounded, wherein said logic circuit comprises a plurality of consecutive adjacent stages, each of said consecutive adjacent stages being connected to said supply rail at said supply voltage and said ground rail at ground; determining that at least a portion of said logic circuit has experienced degradation due to bias temperature instability; and responsive to said determining, operating said logic circuit in a power napping mode, with said supply voltage coupled to said ground rail of said circuit, with said supply rail of said circuit grounded, and with primary inputs of said circuit toggled between logical zero and logical one at low frequency, such that said plurality of consecutive adjacent stages are connected to said supply rail at ground and said ground rail at said supply voltage and such that n-type field effect transistors of said consecutive adjacent stages recover when said primary inputs are at said logical zero without stressing p-type field effect transistors of said consecutive stages, and such that p-type field effect transistors of said consecutive adjacent stages recover when said primary inputs are at said logical one without stressing n-type field effect transistors of said consecutive stages.