发明名称 JUNCTION FIELD EFFECT TRANSISTOR
摘要 In a high voltage JFET, a p-floating region is provided in the surface layer of an n-drift region, thereby increasing the resistance R of the n-drift region and minimizing the voltage divided at a pn junction. This makes it possible to improve ESD capacity without increasing device size and without making the cutoff current smaller.
申请公布号 US2015200309(A1) 申请公布日期 2015.07.16
申请号 US201414560516 申请日期 2014.12.04
申请人 Fuji Electric Co., Ltd. 发明人 KARINO Taichi;SUMIDA Hitoshi
分类号 H01L29/808 主分类号 H01L29/808
代理机构 代理人
主权项 1. A junction field effect transistor, comprising: a second conductivity type drain region formed in a surface of a first conductivity type semiconductor region; a second conductivity type drift region contacting said drain region and formed in the surface of the semiconductor region; a second conductivity type source region contacting said drift region and formed in the surface of the semiconductor region separated from the drain region; an interlayer insulating film formed on the semiconductor region; and a first conductivity type floating region formed in a surface of the drift region separated from the source region, said floating region being electrically floating.
地址 Kanagawa JP