发明名称 METHODS AND ARRANGEMENTS FOR A CHECK SEQUENCE
摘要 According to various aspects of the present disclosure, medium access control (MAC) sublayer logic of a device or a system may generate and implement a preamble structure of a data unit including a signal field which includes a four-bit cyclic redundancy check sequence providing a Hamming distance of two. The signal field portion of the preamble structure may include information related to a plurality of physical layer parameters used for wireless communication of the data unit. The preamble structure may be stored on a machine-accessible medium. The preamble may be generated by a data unit builder of the device, which may further receive a frame including a data payload, and encapsulate the frame with the preamble portion to generate the data unit. A transmitter coupled with the data unit builder may then wirelessly transmit the data unit using an antenna array.
申请公布号 EP2893664(A1) 申请公布日期 2015.07.15
申请号 EP20130836108 申请日期 2013.06.25
申请人 INTEL CORPORATION 发明人 TETZLAFF, THOMAS;PARK, MINYOUNG
分类号 H04L1/00 主分类号 H04L1/00
代理机构 代理人
主权项
地址
您可能感兴趣的专利