Method and apparatus for reading variable resistance memory elements

摘要

In some embodiments, detecting resistance in a resistive memory cell may be done using a pulse edge. For example, a pulse may be applied through a resistive memory data cell and another through a reference delay circuit to determine which path has the larger delay in order to determine the resistive state of the data cell in question.

主权项

1. A chip, comprising:
a variable resistance memory cell; a reference delay circuit; and a detector coupled to the variable resistance memory cell and reference delay circuit to determine whether a pulse from the variable resistance memory cell arrives before a pulse from the reference delay circuit, wherein the pulse from the variable resistance memory cell has a leading edge that transitions from a high level to a low level, and wherein the pulse from the reference delay circuit has a leading edge that transitions from a high level to a low level.