Memory cells having a common gate terminal

摘要

Arrays of memory cells having a common gate terminal and methods of operating and forming the same are described herein. As an example, an array of memory cells may include a group of memory cells each having a resistive storage element coupled to a select device. Each select device includes a first terminal, a second terminal, and a gate terminal, where the gate terminal is common to each memory cell of the group.

主权项

1. An array of memory cells, comprising:
a group of memory cells, each including a resistive storage element coupled to a select device, wherein the group includes at least three memory cells such that at least two of the three memory cells are physically connected to a first sense line and at least two of the three memory cells are physically connected to a first access line; wherein each select device includes a base semiconductor material, a first terminal, a second terminal, and a gate terminal; and wherein the gate terminal of each select device is formed from a continuous gate terminal material that surrounds each of the base semiconductor materials, and wherein the gate terminal of each select device is common to each memory cell of the group.