Integrated circuit and clock frequency control method of integrated circuit

摘要

A bus interface includes a chip select terminal, a first transmission bus terminal, a second transmission bus terminal, and a clock control device. The chip select terminal transmits a chip select signal to start the data transmission. When the data transmission starts, the first transmission bus terminal sends data to the second device, and the second transmission bus terminal sends the data from the second device to the first device. The clock control device includes a frequency processing unit and a transmission clock generating unit. The frequency processing unit outputs a clock control signal when a frequency to set value changes. The transmission clock generating unit receives the clock control signal and generates a transmission clock in accordance with the frequency setting value.

主权项

1. An integrated circuit electrically connected to a first device, wherein the integrated circuit comprises:
a chip select terminal for transmitting a chip select signal to start data transmission; a first transmission bus terminal for sending data to a second device when the data transmission starts; a second transmission bus terminal for sending the data from the second device to the first device when the data transmission starts; and a clock control device, comprising:
a frequency processing unit for outputting a clock control signal when a frequency setting value changes; anda transmission clock generating unit comprising a clock counter, wherein the transmission clock generating unit receives the clock control signal and counts a cycle number of a system clock through the clock counter and the frequency setting value to generate a transmission clock with a frequency variable in accordance with the frequency setting value, wherein the transmission clock generating unit comprises:
a logic comparator for receiving and comparing the frequency setting value with the cycle number of the system clock, wherein the logic comparator asserts a clock enable signal when the cycle number of the system clock is equal to the frequency setting value;a transmission cycle counter for outputting the transmission clock when the clock enable signal is asserted;a transmission cycle logic circuit for detecting whether the transmission of a packet group is finished;a first logic operation circuit for asserting a frequency variation flag when the clock control signal is asserted and the packet group had been delivered; andan operation value register for loading the frequency setting value from the frequency setting register and outputting the frequency setting value to the logic comparator, wherein the operation value register loads the frequency setting value from the frequency setting register when the frequency variation flag is asserted.