| 摘要 |
This invention comprises a layout method to effectively protect logic circuits against soft errors (non-destructive errors) and circuit cells, with layout, which are protected against soft errors. In particular, the method protects against cases where multiple nodes in circuit are affected by a single event. These events lead to multiple errors in the circuit, and while several methods exist to deal with single node errors, multiple node errors are very hard to deal with using any currently existing protection methods. The method is particularly useful for CMOS based logic circuits in modem technologies (.ltoreq.90 nm), where the occurrence of multiple node pulses becomes high (due to the high integration level). It uses a unique layout configuration, which makes the circuits protected against single event generated soft-errors. |
| 主权项 |
1. A sequential logic cell comprising:
four inverter circuits, each of the four inverter circuits comprising one p-type MOSFET having a gate, one n-type MOSFET having a gate, and one output, wherein the four inverter circuits are connected as a Dual Interlocked Cell (DICE), wherein for each inverter circuit, the gate of the p-type MOSFET is coupled to the output of a first of three remaining inverter circuits and the gate of the n-type MOSFET is coupled to the output of a second of the three remaining inverter circuits, wherein the first and second inverter circuits are different; wherein the DICE comprises four nets, wherein each of the inverter outputs is coupled to one of the four nets, wherein a first net and a second net comprise a voltage state, and wherein a third net and a fourth net comprise an inverse voltage state, and wherein each net comprises a p-type drain contact area and an n-type drain contact area; wherein each of the p-type contact areas and the n-type contact areas are placed along a line, wherein the line comprises a plurality of adjacent contact areas comprising a first contact area and a second contact area; wherein for each pair of adjacent contact areas, if a first adjacent contact area and a second adjacent contact area both comprise p-type drain contact areas or both comprise n-type drain contact areas, the first adjacent contact area and the second adjacent contact area are coupled to nets comprising opposite voltage states; and wherein for each pair of adjacent contact areas, if the first adjacent contact area and the second adjacent contact area comprise one p-type drain contact area and one n-type drain contact area, the first adjacent contact area and the second adjacent contact area are coupled to nets comprising similar voltage states. |
