Integrated split gate non-volatile memory cell and logic structure

摘要

A method of making a semiconductor structure includes forming a select gate and a charge storage layer in an NVM region. A spacer select gate is formed by depositing a conformal layer followed by an etch back. A patterned etch results in leaving a portion of the charge storage layer over the select gate. A dummy gate structure formed in a logic region has a dummy gate surrounded by an insulating layer. Performing chemical polishing results in the top surface of the charge storage layer being coplanar with top surface of the dummy gate structure. Replacing a portion of the dummy gate structure with a metal logic gate which includes a further chemical mechanical polishing results in the top surface of the charge storage layer being coplanar with the metal logic gate.

主权项

1. A method of making a semiconductor structure using a substrate having a non-volatile memory (NVM) region and a logic region, comprising:
forming a select gate over the substrate in the NVM region; forming a charge storage layer over the substrate including over the logic region and the NVM region, wherein over the NVM region includes over the select gate; forming a conformal conductive layer over the charge storage layer including over the logic region and the NVM region, wherein over the NVM region includes over the select gate; etching the conformal conductive layer to form a control gate adjacent to a sidewall of the select gate; forming a mask over the charge storage layer, the control gate, and a portion of the select gate; performing a patterned etch of the charge storage layer using the mask to leave a portion of the charge storage layer over the select gate and under the control gate and to remove the charge storage layer from the logic region; forming a dummy gate structure in the logic region having a dummy logic gate surrounded by an insulating layer; performing chemical mechanical polishing to remove the portion of the charge storage layer over the select gate and to result in a top surface of the NVM region being coplanar with a top surface of the logic region; and replacing a portion of the dummy gate structure with a metal gate.