发明名称 |
Signal multiplexing device |
摘要 |
A signal multiplexing device includes a selector (1) that selects one of input data (4) and a complementary signal (16), a clock recovery circuit (30a) that adjusts the phase of a recovered clock (7) to the timing of the output signal of the selector (1), and a flip-flop circuit (3) that performs identification/recovery of the output signal of the selector (1) based on the recovered clock (7). The frequency of the complementary signal (16) is an integral submultiple of the frequency of the recovered clock (7). The selector (1) selects the complementary signal (16) during part of the no-signal period of the input data (4). |
申请公布号 |
US9083476(B2) |
申请公布日期 |
2015.07.14 |
申请号 |
US201213980570 |
申请日期 |
2012.01.20 |
申请人 |
NIPPON TELEGRAPH AND TELEPHONE CORPORATION |
发明人 |
Katsurai Hiroaki;Kamitsuna Hideki;Ohtomo Yusuke |
分类号 |
H04J3/06;H03L7/08;H03L7/18;H04L7/033;H04L7/00;H04L7/027 |
主分类号 |
H04J3/06 |
代理机构 |
Blakely Sokoloff Taylor & Zafman |
代理人 |
Blakely Sokoloff Taylor & Zafman |
主权项 |
1. A signal multiplexing device comprising:
a selection circuit that selects and outputs one of an input signal and at least one complementary signal of the input signal; a clock recovery circuit that adjusts a phase of a recovered clock to a timing of an output signal of said selection circuit and outputs the recovered clock in synchronism with the output signal of said selection circuit; and an identification circuit that performs identification/recovery of the output signal of said selection circuit based on the recovered clock, wherein a frequency of the recovered clock equals a frequency of the input signal, and a frequency of the complementary signal is an integral submultiple of the frequency of the recovered clock, and said selection circuit selects the complementary signal during part of a no-signal period of the input signal. |
地址 |
Tokyo JP |