Semiconductor memory device and writing method of ID codes and upper addresses

摘要

A semiconductor chip D1 of a flash memory which is stacked together with other semiconductor chips D2˜DN to form a multi-chip package (MCP), including a memory cell array 20 of the flash memory for storing an ID code and an upper address, wherein the ID code is written into the a fuse data region 20F of the memory cell array 20 before the assembly process. According to the invention, ID codes and upper addresses can be assigned and written to each of the semiconductor chips of a multi-chip package easily without increasing the size of the semiconductor chips in comparison with the prior art.

主权项

1. A semiconductor memory device which is stacked together with other semiconductor memory devices to form a multi-chip package, the semiconductor memory device comprising:
a non-volatile memory means storing an ID code and an upper address, and a first comparing means responding to an ID code match command which is input from an external device to the semiconductor memory device and indicates a predetermined ID code, searching for the ID code of the semiconductor memory device, comparing the predetermined ID code and the ID code, and outputting a comparison result, wherein the ID code is written into the non-volatile memory means before the assembly process, the semiconductor memory device is a flash memory, and the non-volatile memory means is a memory type fuse element in a memory cell array of the flash memory, when the first comparing means outputs the comparison result showing the predetermined ID code and the ID code are consistent with each other, the semiconductor memory device has an active status to be allowed to receive other commands from the external device until the semiconductor memory device receives an ID release command input from the external device and indicating access from the external device is finished, and when the first comparing means outputs the comparison result showing the predetermined ID code and the ID code are not consistent with each other, the semiconductor memory device goes into a standby status to wait for the ID code match command or the ID release command.