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发明名称
降低随机良率缺陷之方法及装置
摘要
申请公布号
TWI492079
申请公布日期
2015.07.11
申请号
TW098146051
申请日期
2009.12.30
申请人
新思科技股份有限公司
发明人
仝仰山
分类号
G06F17/50
主分类号
G06F17/50
代理机构
代理人
邓民立 台北市大安区罗斯福路2段79号7楼之2
主权项
一种降低随机良率缺陷之方法,包含:根据一设计布局进行临界面积分析,而据以得到各待更正线路之开路临界面积及短路临界面积;将各该待更正线路之开路临界面积及短路临界面积分别运算,并加总得到一加总值;以及对各该待更正线路同时进行线路延展及线路加宽之不同调整而改变该加总值,从而得到该些待更正线路之线路延展及线路加宽之最佳化更正组合。
地址
美国
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