Coarse Data Aligner

摘要

An alignment circuit is disclosed. In one embodiment, the circuit includes a shift register having a plurality of serially-coupled storage elements each configured to receive a first signal on a respective clock input, wherein a data input of a first one of the serially-coupled storage elements is configured to receive a second signal. The circuit further includes a detector configured to detect a position of a logical transition based on data shifted into the shift register and an encoder configured to generate selection signals based on the position of the logical transition. A multiplexer tree configured to select a bit position of one of the plurality of serially-coupled storage elements based on the selection signals, wherein an output of the multiplexer tree is a third signal that is a version of the second signal.

主权项

1. A circuit comprising:
a shift register having a plurality of serially-coupled storage elements each configured to receive a first signal on a respective clock input, wherein a data input of a first one of the serially-coupled storage elements is configured to receive a second signal; a detector configured to detect a position of a logical transition based on data shifted into the shift register; to an encoder configured to generate selection signals based on the position of the logical transition; and a multiplexer tree configured to select a bit position of one of the plurality of serially-coupled storage elements based on the selection signals, wherein an output of the multiplexer tree is a third signal that is a version of the second signal.