发明名称 MATRIX OF ON-CHIP ROUTERS INTERCONNECTING PLURAL PROCESSING ENGINES AND METHOD OF ROUTING USING THE SAME
摘要 PROBLEM TO BE SOLVED: To provide a chip comprising a flexible and scalable network.SOLUTION: The network includes a plurality of processing engines 105 and a matrix of on-chip routers 110. Each of the on-chip routers 110 is communicatively coupled with a distinct group of the processing engines 105 and with on-chip routers 110 nearest to that on-chip router 110. The on-chip routers 110 include input ports, output ports, and an output port arbiter corresponding to the output ports. The output port arbiter uses a global grant vector shared by all output port arbiters of that on-chip router and a local grant vector unique to that output port arbiter to grant a query request from one of the input ports.
申请公布号 JP2015128294(A) 申请公布日期 2015.07.09
申请号 JP20140263372 申请日期 2014.12.25
申请人 XPLIANT INC 发明人 ANH T TRAN;GERALD SCHMIDT;TSAHI DANIEL;NIMALAN SIVA
分类号 H04L12/937 主分类号 H04L12/937
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