Hazard detection and elimination for coherent endpoint allowing out-of-order execution

摘要

A coherence maintenance address queue tracks each memory access from receipt until the memory reports the access complete. The address of each new access is compared against the address of all entries in the queue. This check is made when the access is ready to transmit to the memory. If there is no address match, then the current access does not conflict with any pending access. If there is an address match, the current access is stalled. The multi-core shared memory controller would then typically proceed to another access waiting a slot to the endpoint memory. Stored addresses in the coherence maintenance address queue are retired when the endpoint memory reports completion of the operation. At this point the access is no longer a hazard to following operations.

主权项

1. A multi-core shared memory controller for managing memory coherence among a plurality of processing cores which may cache data and a shared memory comprising:
a plurality of input ports, one corresponding to each one of the plurality of processing cores, for receiving memory access requests to the shared memory including read address, write address and write data from the corresponding processing core; a coherence maintenance address queue having a plurality of entries, each entry storing an address of an access request committed to the shared memory and an assigned ID tag; an ID allocation block coupled to said coherence maintenance address queue assigning an available ID tag from a set of ID tags to an access committed to the shared memory for storage in said coherence maintenance address queue and retiring a coherence maintenance address queue entry upon receipt of a completion signal from the shared memory indicating completion of the corresponding access; and a comparator coupled to said input ports and said coherence maintenance address queue and receiving an address of a memory access request, said comparator comparing the address of the memory access request with all addresses stored in said coherence maintenance address queue and generating a hazard stall signal if the address of the memory access request matches any address stored in said coherence maintenance address queue.