Fractional clock generator

摘要

Various embodiments of the invention allow the generation of an output clock signal that comprises a frequency that is a fractional frequency of an input clock signal and is adjusted with respect to an input signal. A fractional clock generator that has high performance output, low power consumption, small area, and good jitter performance is presented.

主权项

1. A fractional clock generator comprising:
a phase splitter that generates phase signals from an input clock signal having a first frequency; a phase generator coupled to receive the phase signals and output a plurality of clock signals of the first frequency, each of the plurality of clock signals comprises has a different phase angle; a phase multiplexer coupled to the phase generator, the phase multiplexer selects a predetermined sequence of the plurality of clock signals in response to receiving a feedback signal, the phase multiplexer configured to generate an output clock signal of a second frequency that can be selected lower and higher than the first frequency; and a selection circuit coupled to the phase multiplexer, the selection circuit comprises a state machine circuit that receives the output clock signal at its input, generates a one-hot signal, and generates the feedback signal that controls the phase multiplexer, the state machine circuit comprising a plurality of flip-flops coupled to each other in a loop configuration such that a data output of each flip-flop is coupled to a data input of a preceding flip-flop.