Synchronous nonvolatile memory device and memory system supporting consecutive division addressing DRAM protocol

摘要

A nonvolatile memory device and system having a nonvolatile memory device accessible with a DRAM protocol for generating a first command signal and a second command signal based on a row address strobe signal and a column address strobe signal and storing an n-bit row address signal based on the first command signal, an n-bit column address signal based on the second command signal, and decoding the n-bit row address signal and the n-bit column address signal to synchronously provide a row selection signal and a column selection signal to a memory cell array.

主权项

1. A nonvolatile memory device, comprising:
a memory cell array including a plurality of memory cells, the plurality of memory cells comprising a first memory cell being connected to a first wordline of a plurality of wordlines and a first bitline of a plurality of bitlines and a second memory cell being connected to a second wordline of the plurality of wordlines and a second bitline of the plurality of bitlines; address input terminals configured to sequentially receive an n-bit row address signal and an n-bit column address signal; a command conversion controller configured to generate a first command signal and a second command signal based on a row address strobe signal and a column address strobe signal; and an address decoder configured to store the n-bit row address signal based on the first command signal, configured to store the n-bit column address signal based on the second command signal, and configured to decode the n-bit row address signal and the n-bit column address signal to synchronously provide a row selection signal and a column selection signal to the memory cell array, wherein the row address strobe signal and the column address strobe signal being generated based on a dynamic random access memory (DRAM) protocol, and wherein the n-bit row address signal and the n-bit column address signal are internally synchronized by latching the bit row address signal, by delaying the latched n-bit row address signal, by latching the n-bit column address signal, and by simultaneously decoding the delayed n-bit row address signal and the latched column address signal such that an active duration of the row selection signal decoded from the n-bit row address signal is at least partially overlapped with an active duration of the column selection signal decoded from the n-bit column address signal.